# THIS FILE IS AUTOMATICALLY GENERATED
# Project: C:\knock_Knock\door_Knock\door_Knock.cydsn\door_Knock.cyprj
# Date: Fri, 02 Nov 2012 22:38:03 GMT
#set_units -time ns
create_clock -name {ClockBlock/clk_bus} -period 41.666666666666664 -waveform {0 20.8333333333333} [get_pins {ClockBlock/clk_bus}]
create_clock -name {ClockBlock/dclk_0} -period 1000 -waveform {0 500} [get_pins {ClockBlock/dclk_0}]
create_clock -name {ClockBlock/aclk_0} -period 4333.333333333333 -waveform {0 2166.66666666667} [get_pins {ClockBlock/aclk_0}]
create_clock -name {CyIMO} -period 333.33333333333331 -waveform {0 166.666666666667} [list [get_pins {ClockBlock/imo}]]
create_clock -name {CyPLL_OUT} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/pllout}]]
create_clock -name {CyILO} -period 1000000 -waveform {0 500000} [list [get_pins {ClockBlock/ilo}] [get_pins {ClockBlock/clk_100k}] [get_pins {ClockBlock/clk_1k}] [get_pins {ClockBlock/clk_32k}]]
create_clock -name {CyMASTER_CLK} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/clk_sync}]]
create_generated_clock -name {ADC_DelSig_1_Ext_CP_Clk} -source [get_pins {ClockBlock/clk_sync}] -divide_by 24 -duty_cycle 50 [list [get_pins {ClockBlock/dclk_glb_0}]]
create_generated_clock -name {ADC_DelSig_1_theACLK} -source [get_pins {ClockBlock/clk_sync}] -divide_by 104 -duty_cycle 50 [list [get_pins {ClockBlock/aclk_glb_0}]]
create_generated_clock -name {CyBUS_CLK} -source [get_pins {ClockBlock/clk_sync}] -duty_cycle 50 [list [get_pins {ClockBlock/clk_bus_glb}]]

set_false_path -from [get_pins {__ONE__/q}]

# Component constraints for C:\knock_Knock\door_Knock\door_Knock.cydsn\TopDesign\TopDesign.cysch
# Project: C:\knock_Knock\door_Knock\door_Knock.cydsn\door_Knock.cyprj
# Date: Fri, 02 Nov 2012 22:38:00 GMT
